In silicon on insulator (SOI) and bulk technologies, for example 32 nm SOI or 28 nm bulk technologies, the FEOL topology, particularly the STI height, is critical for encapsulation of a high-k/titanium nitride (TiN) gate stack, especially for gate first integration. However, STI step height is difficult to control through various FEOL processes after formation of the STI region. As illustrated in FIGS. 1A through 1C, STI regions are conventionally formed by forming a pad oxide layer 101 to a thickness of 3 nm to 10 nm on an upper surface of a substrate, for example SOI substrate 103 (formed of a substrate 105, buried oxide layer 107, and silicon layer 109), forming a silicon nitride (SiN) polish stop layer 111 on the pad oxide 101, forming a photoresist or hard mask 113 over the active areas 115, etching a trench 117 in the silicon layer 109 between active areas 115, stripping the resist or hard mask 113, cleaning, forming an oxide liner (not shown) in the trench 117, filling the trench 117 with a field oxide (FOX) such as silicon oxide, forming STI regions 119, and performing chemical mechanical polishing (CMP) stopping on the pad nitride 111.
Once the STI regions are formed, pre-gate implants in the active areas 115 may damage the FOX, thereby causing an increased wet etch rate of the FOX. Also, oxide mask removal during channel silicon germanium (c-SiGe) formation may cause step height differences on the FOX between the PFET and NFET. Stripping either the PAD oxide or a sacrificial oxide formed on a pre-damaged FOX may then cause further damage to the FOX. Divots may then be formed in the surface of the STI regions. The uneven FEOL topology results in an uncontrolled gate taper profile, which in turn results in an exposed high-k/TiN layer, as the encapsulation layer will be opened at the tapered sidewall. Subsequent wet etches can remove parts of the TiN from the gate stack which results in threshold voltage (Vt) shifts, reducing yield.
Efforts have been made to flatten the FEOL topology by adjusting deglaze. Deglaze moves the STI oxide surface above, flush with, or below the active silicon at polysilicon deposition. Further efforts to flatten the FEOL topology include adjusting NFET and PFET mask removal to recover the N-to-P STI topology delta that is created during cSiGe integration. However, neither process can prevent the FOX damage by implants, and, therefore, the increased wet etch rate. Further, divot formation due to oxide loss post STI SiN strip, caused by isotropic wet etch steps such as sacrificial oxide clean and wet pre dual gate oxide clean and dual gate oxide etching, cannot be suppressed. Although increased cure anneals (such as 1150° C.) may reduce divot formation, they require a high thermal budget which causes wafer warpage and a negative impact on the resulting devices.
A need therefore exists for methodology enabling a divot free, zero step height STI topology, and the resulting semiconductor device.